Passive UHF RFID Tags

This article is one of the most in-depth technical references I've ever read. It is chapter 5 from “The RF in RFID: Passive UHF RFID in Practice” written by Daniel M Dobkin printed with permission from Newnes, a division of Elsevier. Copyright 2008.

I've had the pleasure of working with Dan for over a year in contributing content for the RFID Essentials suite of e-learning courses developed by RFID Revolution. Dan helped create the YouTag Virtual Workshops. Anyone that spends more than a few minutes with Dan will quickly realize he knows a lot about the RF in RFID. Dan also has a PhD in Physics from Stanford. After reading this chapter, you will understand why we consider Dan a subject matter expert and trusted adviser in our community.

Visit www.newnespress.com or call 1-800-545-2522 to purchase the book. This article includes Chapter 5.

Power and Powerlessness

Tags identify objects. When the objects are very expensive, the cost of the tags is of little consequence, but their endurance is of great import, since expensive objects, and our interest in them, are usually also long lived. When the objects are cheap, the tags must be cheaper. These are the fundamental dynamics of tag design.

As a consequence, tags that are intended to label long-lived, expensive objects (typically viewed as assets on someone’s books) are usually active tags, with their own radio transmitter and receiver, powered by a local battery. Since battery technology has progressed very slowly relative to semiconductor technology, the key issues in designing a active tag are to minimize the duty cycle—the proportion of time during which the tag is doing something other than sleeping—and to minimize the power required both to support the active state and the sleep or idle state. While these are not trivial design challenges, the technology used to fabricate an active tag is substantially similar to that used in other radios including the reader radio: discrete components and ICs are soldered to a printed circuit board, with the whole attached to a compact antenna and placed within a plastic housing.

Passive tags are mostly meant to identify inexpensive objects, and must thus, submit to an economic asceticism that eschews such luxuries. Conventional batteries are far too bulky and expensive to be considered. A conventional radio transmitter or receiver, with the complex and expensive oscillators, mixers, and synthesizers is out of the question. Only inexpensive, low-speed circuitry and simple logic are permitted to us if the tag is to be powered by the pittance of microwatts available at several meters distance from a reader. Instead of a proper transmitter, a switch to change the impedance presented to an antenna must suffice. A single IC is usually the only electrical &rar; component to be placed on the tag, and thus, this circuit must be a custom design solely for its specialized application. The expense of creating such an application-specific integrated circuit (ASIC) implies that only large volume usage can provide an economic return to the company responsible for it.

Between these extremes lie semipassive tags, possessed of a battery but bereft of a radio. To date, such tags have typically been constructed for specialized applications with moderate volumes, such as auto tolling, and use fairly conventional fabrication and design approaches, with special attention to duty cycle just as for active tags.

A greatly simplified diagram of the electrical constituents of a passive tag is depicted in Figure 5.1. The radio signal at around 900 MHz from the reader is converted by the antenna into an alternating current, from which the tag must extract both power and information. The tag must then interpret the resulting data, possibly requiring writing data to nonvolatile memory, and modulate the load presented to the antenna in order to change the backscattered signal returning to the reader.

In what follows, we shall examine a few of the special challenges of designing and manufacturing a passive UHF tag:

How is power to be extracted from the high-frequency radio signal?
How can we simultaneously acquire whatever data the reader has sent?
How do we send back information to the reader?
How is the resulting chip designed and fabricated?
How is a completed tag assembled from the chip and other parts?

RF to DC

To operate, a tag IC needs not just power, but direct-current (DC) power: a source of voltage that is roughly constant in time, of magnitude from 1 to 3 V depending on the type of transistors used in the circuitry, and capable of supplying a few tens of microamps of current. The tag needs to get this DC power from an incoming RF signal whose polarity changes about 900 million times per second, and with the proviso that at a few meters from the reader, a small tag antenna provides an open-circuit voltage of only about 0.1–0.3 V.

To change alternating (AC) voltages to DC, we need an electrical component that treats positive and negative polarities differently: a diode. The left side of Figure 5.2 shows the idealized version of a diode: a component that allows electrical current to flow only in one direction. The right side of the figure shows a more realistic view of a diode’s characteristics: in the allowed (forward) direction current turns on slowly until some turn-on voltage is reached, thereafter increasing more rapidly. In the blocked (reverse) direction, a small leakage current flows, increasing as reverse voltage is increased.

The actual current flow through a diode is exponential in the voltage; a reasonable approximation is:

where I is current, V is voltage, q the charge on an electron, k is Boltzmann’s constant and T the absolute temperature. I0 is a constant characteristic of the particular type of diode in question. The quantity kT/q is about 0.026 V at room temperature, so if we increase the applied voltage by 1 V, we increase the current through the diode by:

That is, the forward current increases very rapidly indeed with voltage. For typical values of current flow, we can treat the current as turning on abruptly at some turn-on voltage Von. Two types of diodes are commonly available in standard IC processing: junction diodes, which have saturation currents I0 around 10−10 to 10−11/cm2 at room temperature, and Schottky diodes with saturation currents 3–7 orders of magnitude larger, corresponding to a reduction in voltage of about 0.2 to 0.3 V for the same current density. (Schottky diodes are more difficult to fabricate and are not always available, or may increase the processing cost when used.) Rectification can also be accomplished using diode-connected transistors, in which the drain is shorted to the gate; in this case, the turn-on voltage is roughly equal to the transistor threshold voltage.

This idealized version of the current-voltage characteristic is shown in Figure 5.3. The current is zero for all voltages less than the turn-on voltage Von, and can become arbitrarily large when the applied voltage exceeds the turn-on voltage. In this view, the diode acts as an ideal switch with an offset voltage. The offset voltage can be estimated from equation (5.1), and varies logarithmically (thus rather slowly) with the DC current required.

Armed with this simplified component model, let us examine the problem of extracting a DC voltage from the RF voltage provided by the antenna to the tag IC. The simplest approach is to place our idealized diode in series with the voltage from the antenna. The result ought to be current flow only in one direction through the diode. We’ll use a capacitor to store the current between RF cycles. (Recall that a capacitor is the analog of a spring. The voltage across the capacitor is proportional to the total amount of current that has flowed into it—the stored charge—analogous to the total extension or compression of a physical spring.) We will represent the remainder of the IC by a load resistor, through which current flows from the capacitor and diode. The whole scheme is shown in Figure 5.4.

Operation of this circuit, treating the diode as an idealized rectifier, is shown in Figure 5.5. When the voltage across the diode is larger than Von, the diode acts like a closed switch, with a voltage offset. A net voltage of (Vpk−Von) appears across the capacitor and resistor, where Vpk is the peak voltage of the signal. During this time, a pulse of current flows into the capacitor to charge it up.

When the voltage on the diode falls below Von, the diode turns off. Current now flows out of the capacitor through the resistor, and the voltage across the resistor decreases. The time required for the capacitor to discharge is equal to the product of the capacitance and resistance, RC. If this time is long compared to the RF cycle time, the supply voltage will be roughly constant during the RF cycle.

Let’s make a simple estimate of the component values required. The RF cycle time is about (1/900 MHz) = 1.1 nanoseconds. Let us assume that the IC consumes about 30 μW from a power supply of 1 V. Since the power dissipated in a resistor is proportional to the square of the voltage and inversely proportional to the resistance, we find

To achieve an RC time constant ten times longer than the RF cycle, we need:

This is a very modest amount of capacitance, even for an IC implementation. So far, it appears easy to convert incoming RF voltages to DC to power the circuit. However, it isn’t sufficient for the DC power to be constant over a single RF cycle: it is necessary that the tag still be powered even when the RF power is briefly switched off to send data to the tag. For plausible data rates, the power could be off for around 10 microseconds. To achieve this RC time constant, we need a capacitance of:

To achieve a reasonably constant supply voltage over the course of an RF cycle, we naturally need much more storage capacitance: on the order of 300 pF to keep the variation in supply voltage small. This is a substantial amount of capacitance and will require about 40 000 to 60 000 square microns of the IC (whose total area is typically 500 000 to 1 000 000 square microns). In addition to just storing enough charge, we also need to distribute the stored charge over the circuit so that those locations that need power at any given moment have it available; otherwise, one transistor switching on will tend to reduce the power supplied to its neighboring transistors, leading to crosstalk and logic errors.

In addition to the problem of providing enough capacitance, we need to provide the full operating voltage of the IC from the available RF voltage from the antenna. This is also challenging, because by reference to Figure 5.5, we can see that the output voltage of the simple rectifier is not the peak voltage of the input but the difference between the peak voltage and the turn-on voltage of the diode. If the incoming peak voltage is less than the diode turn-on voltage, the diode will never turn on and no power will be delivered to the circuit. Even when the incoming voltage is large enough to get through the diodes, the sacrifice of Von is painful: an IC needs 1 or 2 V to run, and the turn-on voltage of a typical diode at the relevant current densities might be around 0.5 V (rather dependent on how much diode area we are willing to devote). All this has to be squeezed out of an antenna that is itself providing only about 0.2 V at a distance of a few meters from the reader antenna. How are we to get enough voltage to run the chip?

The first tool we can make use of is reactive matching. The voltage provided by the antenna is associated with a specific source resistance and reactance; typically, the source resistance varies from a few tens to a few hundred ohms depending on the antenna configuration. The IC draws a few microamps at a volt or two, so the dissipative part of the IC appears as a rather larger resistance (typically 1–10 kΩ). By using inductors or capacitors to match the source and load, we can theoretically gain an increased voltage proportional to the square root of the ratio of these impedances. However, it is not practical to extend this approach indefinitely. Real matching elements have finite loss, and a very high Q also results in narrow bandwidth. For example, let us assume that wish a tag to operate over the whole region of frequencies in use worldwide, that is from 860 to 960 MHz. The relative bandwidth ought to be around (100/900) = 11%, so the matching network should have a quality factor around 1/0.11 = 9 or 10. Therefore, we can achieve an increase of 5- to 10-fold in the antenna voltage using reactive matching.

A very common approach to obtaining higher voltages from a rectifier is the use of a charge pump: a number of diodes connected in series so that the output voltage of the array is increased. The simplest sort of charge pump, a voltage doubler, is shown in Figure 5.6. Two diodes are connected in series, oriented so that forward current must flow from the ground potential to the positive terminal of the output voltage VDD. A capacitor prevents DC current from flowing between the antenna and the diodes, but stores charge and thus, permits highfrequency currents to flow. A second capacitor stores the resulting charge to smooth the output voltage.

When the RF voltage is negative and larger than the turn-on voltage, the first diode is on (Figure 5.7). Current flows from the ground node through the diode, causing charge to accumulate on the input capacitor. At the negative peak, the voltage across the capacitor is the difference between the negative peak voltage and the voltage on the top of the diode. The output (right) plate of the capacitor is (Vpk − Von) more positive than the RF input.

When the RF input becomes positive, the first diode turns off and the second (output) diode turns on (Figure 5.8). The charge that was collected on the input capacitor travels through the output diode to the output capacitor. The peak voltage that can be achieved is found by adding the voltage across the input capacitor, which we found above, to the peak positive RF voltage and subtracting the turn-on voltage of the output diode:

In the limit where the turn-on voltage can be ignored (e.g. when the input voltage is very large), the output DC voltage is double the peak voltage of the RF signal, from which fact the circuit derives its name. The actual output voltage depends on the amount of current drawn out of the storage capacitor during each cycle, that is on the value of the load resistance (not shown here).

To produce higher output voltages, we can provide additional stages of multiplication to produce a Dickson charge pump. A two-stage configuration is shown in Figure 5.9; in the case of ideal diodes with negligible turn-on voltage, the output would be four times larger than the peak RF input voltage. In general, for N stages we find:

It is tempting to imagine that one could continue to add as many stages as required to convert even the most modest input voltage into something adequate to power the IC, but as we add stages, we encounter diminishing returns. A very simple analysis of the problem is shown in Figure 5.10. All the DC current must flow through all the diodes in series, so as we add more stages, we waste more and more power in the turn-on voltage of the diodes:

The power efficiency of the charge pump thus decreases as the number of stages increases for a given turn-on voltage and output voltage:

(This analysis turns out to be a bit optimistic for the single- and two-stage cases if substrate loss—current flowing into the bulk of the silicon wafer due to the capacitance of the diode to the substrate—is significant.)

The resulting behavior is shown in Figure 5.11. We can see that the more stages we add (to enable the IC to run with a smaller RF power and thus extend the nominal range), the less efficient the charge pump becomes.

A reasonable approach to estimating the number of stages is to extract an equivalent resistance from the load, given the total power calculated above:

where the input voltage is adjusted to produce the requisite load voltage from equation (5.7). Roughly speaking, the largest resistance that can be matched to the antenna is Q2 times larger than the radiation resistance of the antenna. For a typical dipole-type antenna, this value is 10–50 Ω, so the largest equivalent resistance that can be optimally matched is around 5 kΩ, assuming the limits on matching mentioned above. (Higher values can be used but at some sacrifice in bandwidth.) We can thus, adjust the number of stages in the charge pump to provide about the right equivalent resistance for the value of Q we expect to achieve in matching.

Several weaker but non-negligible effects are important in arriving at a final design. The area of the diodes has a weak (logarithmic) effect on the turn-on voltage and thus on the efficiency, so one is tempted to make the diodes large. However, the diode capacitance grows linearly with the diode area, and since the equivalent resistance of the charge pump is fixed (by the power and voltage targets, as described above), as the diodes are made larger the capacitor starts to draw a substantial reactive current. The capacitance is also voltage dependent (increasing noticeably as the diodes are turned on), and the variation in capacitance degrades the performance of the matching network, particularly for narrow band, high-Q networks. A charge pump with more stages has smaller capacitance variations because the peak voltage across each diode is closer to the turn-on voltage; a typical change for a junction diode is around 25–30% of the zero-bias capacitance. Larger diodes contribute more capacitance but need less peak forward voltage for the same current, so the capacitance variation grows rather more slowly than the capacitance itself. A plausible guideline is that the change in reactance of the equivalent input capacitance be comparable to the equivalent resistance of the load, leading to an input capacitance of around 0.25–0.5 pF for typical parameter values. The exact results are, of course, sensitive to the details of the process technology used.

Even from this rough modeling approach, it is clear that key leverage in operating at higher efficiencies and lower power lies in reducing the turn-on voltage of the diodes comprising the charge pump (ideally without excessive increases in diode capacitance), and it can be expected that progress along those lines will continue to improve passive chip performance.

Getting Started, Getting Data

Once power is available from the charge pump, it is often helpful to reset the state of the logic circuitry. An example of a circuit to send this power-on reset (POR) signal is depicted in Figure 5.12. The circuit has two branches, each with an NMOS and PMOS transistor in series. The gates of the left branch transistors are connected to the drains of the right branch, and vice versa. Recall that an NMOS device turns on when the gate is positive with respect to the source (thus attracting electrons) and a PMOS device turns on when the gate is negative (attracting holes). If, for example, the right side gate connection becomes a bit more positive than the source, the NMOS device begins to turn on and the PMOS device becomes more resistive. This causes the voltage on the common drains to become more negative, resulting in the left-hand PMOS device turning on and the left-hand NMOS device turning off. The left-hand drains thus become more positive, enhancing the original displacement. The NOR (not-OR) gate output is high when the inputs are different, so since as this circuit turns on, it rapidly assumes opposite states on the two branches, the NOR gate launches a positive-going pulse to reset the remainder of the circuit (POR).

The signal from an RFID reader is amplitude modulated to convey information to the tags. In order to demodulate the signal, we need to create a baseband voltage whose magnitude is proportional to the peak voltage of the reader signal: the envelope of the RF signal. We have already created a circuit that will do the trick (Figure 5.4), if we choose a storage capacitance value C that provides a storage time long compared to the RF cycle (around 1.1 nanoseconds) but short compared to the length of the data-carrying modulation pulses (one to several microseconds). If necessary (if the antenna is a DC-open or is capacitively coupled), we may provide a resistor to provide a discharge path for the storage capacitance; the values of the capacitor and resistor are chosen to provide a time constant RC of a few nanoseconds. To provide a larger signal voltage for a given RF peak voltage, we can construct a multistage charge pump like that of Figure 5.9, though again happily the requirements are much less demanding, since we need deliver only enough voltage to allow the subsequent circuitry to distinguish between the RF power-high and RF power-low conditions of the reader signal. It may also be useful to construct a similar circuit with a longer time constant, to extract a voltage corresponding to the average RF power over many symbols. A simple circuit suitable for these purposes is shown in Figure 5.13.

Once we have obtained a low-frequency voltage proportional to the RF power, we need to extract information from it. If the data is, for example, PIE coded, what we need to figure out is how long the signal remains high between pulses: a long RF-high period represents a binary-1 and a short RF-high period represents a binary-0 (see for example Figure 3.7). One simple approach is shown in Figure 5.14. The output of the envelope-detect circuit is directed to a trigger circuit, with an optional current source or other provisions to set the threshold for the trigger. The trigger thus changes state at the beginning of an RF-on pulse, and resets an integrator, which then starts accumulating charge while the voltage is high. The output of the integrator grows linearly with time as long as a signal is applied to its input; on the next rising edge of the RF signal, the integrator output is large if the power was high for a long time, or smaller if the RF-high time was short. That output is applied to a discriminator, which then outputs a 1 or 0 depending on the duration of the RF-high period, just as desired.

Recall that a radio receiver typically includes filtering to select the desired channel, and minimize noise and interference from other transmitters. A passive tag has no such luxurious amenities. Since there is no local RF oscillator or mixer, there is no conversion operation to allow for channel filtering: all received signals at any RF frequency are converted to baseband by the charge pump. The tag antennas provide some frequency selectivity but will generally cover at least the 902–928 MHz ISM band for United States operation. Thus, any transmission in this band, including not only other RFID readers but cordless phones, wireless networks, cell phones and cell basestations, alarm systems, badly grounded spark plug wires, and any other nearby RF radiators all blast right into the IC’s receiver.

Talking Back

Passive tags use modulation of the power scattered by the tag antenna to reply to the reader. In our earlier discussions of backscatter modulation, we imagined a very simple scheme in which the IC simply interrupts current flow through the antenna to modulate the scattered power (see for example Figure 3.15). Let’s take a closer look at how one might modulate the behavior of the antenna and what the consequences are. The three questions we need to address are:

How much scattered power can we send back to the reader?
What effect do we have on the power absorbed by the (IC) load?
How hard is it to implement a given scheme?

Let us first examine the limiting cases of the loads that can be presented to the antenna. These are shown schematically in Figure 5.15. Note that in this and subsequent diagrams, we show an antenna connected to a ground node, which is defined to be at zero voltage. In practice, most tag antennas are symmetric and there is no easy way to define a true “zero” voltage, but the principles are the same, and it is much easier to discuss the problem in this single-ended configuration, rather than the actual balanced or differential connection.

In normal operation, we shall assume that the IC is matched to the antenna: that is, the antenna and IC have been adjusted so that the largest possible power is delivered to the IC. We shall momentarily specify in more detail what this implies about the behavior of the system.

When an open circuit is presented to the antenna, the path to ground is blocked and no current flows in the antenna; since there is no current flowing, no power is radiated (backscattered) in this state. (Real antennas are not quite so simple and do scatter some power even when they are presented with an open circuit load, and real antenna designs don’t quite correspond to the configuration shown here.)

When a short circuit is presented to the antenna, current flows readily to ground without encountering any resistance or creating any voltage. It may be inferred that, in this case, a large antenna current flows and substantial scattered power results.

In order to examine the use of these three states for modulation in a quantitative fashion, we need to construct an equivalent circuit for an antenna. We’ll use the very simplified circuit in Figure 5.16. The antenna is represented by a voltage source Vant, arising from the impinging RF electric field from the reader, and a radiation resistance Rrad, so named because it arises not from the electrical resistance of the metal of which the antenna is constructed but from the power lost in the scattered waves that result when current flows in the antenna. The antenna current must flow also through a load consisting of the (constant) load resistance due to the IC’s power supply (the charge pumps we discussed in Sections 5.2 and 5.3 above), with provisions for opening or closing switches to present either an open or a short to the antenna.

The power delivered to the radiation resistance (and thus scattered back into the world) is proportional to the product of the square of the current and the resistance, like any other resistor. When the switches are in the default configuration Figure shown, the same current must flow through the load resistor. The total current is readily found from Ohm’s law (see Appendix 3):

When the load resistance is very small compared to the radiation resistance, there isn’t much voltage across the load and little power is delivered to the load. When the load resistance is much larger than the radiation resistance, all the voltage appears across the load, but little current flows, so again not much power is delivered to the load. It is easy to show that the optimum power transfer—the matched condition—occurs when the values of the source and load resistance are equal. This is the state to which all our previous calculations of the power available from an antenna referred. Note that as a consequence, in the matched condition, the power dissipated in the load is equal to the power dissipated in the radiation resistance—that is, a matched antenna scatters as much power as it receives. Let us denote this power Pav, the available power. This is the baseline backscattered signal of the unmodulated, matched antenna. We must now examine how this signal changes when we change the load.

Let us first examine the use of an open circuit load for modulation (Figure 5.17). In order to transmit information back to the reader, we can switch the antenna between state 1, in which the antenna sees the matched load of the IC, and state 2, in which an open circuit is presented to the antenna. As we noted in Chapter 3, typical tag modulation approaches, such as FM0, switch symmetrically between the possible tag states, so the tag will spend an equal amount of time in state 1 and state 2.

The equivalent signal power is due to the change in current between the modulated and unmodulated states; the peak power is thus equal to the available power, and if the states are equally likely it is on half the time. Therefore the average backscattered signal power is half the available power

)

The power delivered to the IC during modulation is the average of that in state 1 (the normal power) and that in state 2 (in which the IC gets no current and so no power):

Another possible approach to modulation is to use a short circuit on the antenna as state 2 (Figure 5.18). In the short circuit condition no power is delivered to the IC, because there is no voltage across it. However, the current in the antenna is doubled relative to the matched case: iant = Vant/Rrad. The signal power is again found from the difference in currents, and is:

That is, the modulation is the same as before even though the peak scattered power is larger. The power delivered to the IC is the same as it was in the previous case:

It is obviously possible to obtain a higher backscattered signal power 2Pav by switching between an open circuit and a short circuit—but in this case no power at all is delivered to the IC! Such a configuration can be considered for a semipassive tag.

Note also that in both cases examined above, the IC power is reduced during modulation. This is an important practical problem. In early tag designs, it was not uncommon for a tag to start its reply to a reader and then run out of juice in the middle of transmitting its ID. Since tags may often be found to be forward-link-limited, it is helpful to consider trading off some backscattered signal for more tag power (though in the real case, the backscattered signal may be lower than the idealized values obtained here). One approach we might consider is to place a resistance in series with the load; we will choose some specific values so that the total power delivered from the antenna is the same in both modulation states (Figure 5.19).

The total power delivered to the (load + modulation resistor) by the antenna is the product of the current and the total resistance:

However, the power delivered to the load resistor (representing the useful power for the IC) is NOT the same:

The average power delivered to the IC is thus:

which is about 0.5 dB better than our simplistic modulation schemes above. The backscattered power is determined by the difference in the currents:

which is about 3.5 dB worse than in the case of the short or open circuit. So modulating the load resistor doesn’t really seem get us much advantage in power to the IC and gives up some backscattered power.

What about the use of a capacitor instead of a resistor to modulate the load? This change in the reactive properties of the load will result in a change in the phase as well as amplitude of the current flowing through the antenna, and thus is phase-shift keying of the tag. An example scheme is shown in Figure 5.20. It will be understood that the positive and negative reactances are likely to be implemented by changing the value of a capacitance. (Recall that there is a capacitance in parallel with the resistive load of the IC, which we have presumed to be removed by the matching network.)

The computation of the currents and powers is rather more involved in this case, but roughly what is going on is that the capacitance changes the phase of the current without changing the amplitude very much. As a consequence, the power delivered to the load resistor is almost the same as in the unmodulated case, but the backscattered power is substantial. The process is depicted graphically in Figure 5.21. The currents are:

The backscattered signal power is due to the difference between these currents:

The voltage across the load can be found by subtracting the voltage across the radiation resistance from the antenna voltage; it has the same magnitude for both states, and is:

and thus, the power dissipated in the load resistor (the IC) is the same in both states:

The performance of these variant modulation schemes is summarized in Table 5.1. Clearly, the best compromise between power delivered to the IC and backscattered power is produced by phase-shift keying. The distinctions are on the order of 1–3 dB. For forward-link limited performance, recall that a 2 dB improvement in power to the IC will only add about 1 dB (10%) to the read range. Similarly, a 3 dB improvement in backscattered power will only provide about 0.8 dB (8%) improvement in reverse-link-limited range since the backscattered power depends on the fourth power of distance. So the distinctions between these approaches are modest in terms of overall tag performance.

We have used very specific examples of ASK and PSK component values for simplicity. In the general case where the component values are allowed to vary from those corresponding to a very small modulated signal to the limit of open and short circuits, it is found that the general conclusions we have arrived at are still applicable: at moderate backscattered power, PSK provides substantially better power delivery to the IC load than ASK, but the backscattered power is always lower than in the extreme case where the load is varied from an open to a short circuit.

It is also worth noting that in the case of the three amplitude-shift-keyed approaches, the power delivered to the load—the rest of the IC—is very dependent on the modulation state, which creates a challenge for the regulation of logic power on the chip, the effect being larger as the modulation efficiency increases. If insufficient regulation and storage are provided, these variations may cause logic errors and degrade the ability of the chip to function properly. Power supply stability may need to be traded against backscatter efficiency and complexity. The use of PSK has the advantage that power delivery to the chip is almost independent of the modulation state, simplifying power management. On the other hand, the effectiveness of all these modulations in producing backscattered power is dependent on the matching approach and antenna parameters. As we will see in Chapter 7, adding a matching network doesn’t change the qualitative results above, but the matching network has a complex effect on the way the signal is created, so that ASK at the tag can become PSK at the antenna and vice versa.

In order to create any sort of useful modulation, the tag needs some sort of clock to tell it what the difference is between a binary ‘1’ and ‘0’, as well as to synchronize the tag’s logic circuitry. The clock is usually implemented as an oscillator circuit, possibly with some provisions for calibrating the clock speed based on the reader preamble. An example for low-power oscillator circuit is shown in Figure 5.22. The circuit begins to oscillate when the enable connection is pulled high (to positive voltage). Operation of the oscillator assumes the availability of reference voltages for PMOS and NMOS devices that ensure that a certain fixed reference current per micron of gate width flows through transistors biased with the cited voltages. The reference voltages are created by tapping off the gate voltage of similar NMOS and PMOS transistors adjusted in a current-mirror configuration to keep their output current constant.

The circuit alternates between the two states depicted in Figure 5.22. In state (a) the output is high. The capacitor is positive, thus holding T2 off and T3 on. The output voltage is also fed back to T1, which connects the NMOS reference transistor to the negative supply voltage. This reference current discharges the positive voltage stored on capacitor C. When the capacitor voltages falls sufficiently, the circuit switches to state (b). T2 turns on and T3 turns off; the output voltage is pulled negative, and fed back to turn T1 off and T4 on. The NMOS reference current terminates, and the PMOS reference current charges the capacitor. Thus, the oscillation frequency is set by the capacitor size, the transistor threshold voltages, and the reference current.

Note that operation of this circuit requires that five transistors operate in series from the difference between +V and −V. This circuit was designed for implementation in a low-threshold-voltage, silicon-on-insulator (SOI) process. A conventional field-effect transistor is manufactured by placing a gate electrode in close proximity to a doped region in a bulk silicon wafer, separated by a thin oxide insulator. The transistor is turned off by adjusting the voltage on the gate to repel the channel carriers (electrons or holes), but some carriers are able to make their way through the underlying silicon from one side of the transistor to the other, contributing to leakage current. In an SOI process, the channel is constructed on top of an insulating layer, so that leakage current in the off state (subthreshold leakage) is reduced, and devices with very small threshold voltages can be used. The cost of SOI processing is generally higher than that of conventional CMOS. In a standard process, the need to supply five threshold voltages in series, which requires the availability of a high supply voltage, will likely limit read range, so this circuit might need to be redesigned for conventional implementation.

Tag IC Overall Design Challenges

Now that we’ve touched on the problems presented by the interface to the physical world, let us turn our attention to the logic, memory, and supporting systems that make the tag responsive to its environment. A rough functional layout of a typical passive tag IC is depicted in Figure 5.23. Around half the chip area is taken up by the logic needed to implement the relevant protocol: about 50 000 transistors for an 18000-6C (EPCglobal Class 1 Generation 2) IC.

We’ve looked at the key RF-related challenges in Sections 5.2–5.4 above. The remainder of the chip operates at baseband frequencies and is generally similar to conventional mixed-signal design. However, there are some special challenges peculiar to the RFID world.

The first challenge is, of course, that of cost. The cost of a chip is dominated by its size if yield is reasonably good. Modern IC manufacturing facilities use 200-mm- or 300-mm-diameter wafers. A standard 200-mm-diameter silicon wafer offers a useful area of about 30 000 square millimeters. (This is a bit less than the total surface area: the region within about 3 mm of the wafer edge is usually not useful for processing.) If a single IC has a useful area of around 1 mm2, we can get about 22 000 chips from a wafer assuming that 90% of the chips are good (that is, the yield is 90%). In small volumes, it costs about $1000 to purchase a processed wafer, so the cost of these ICs would be roughly $0.05 per chip. The use of 300-mm wafers increases the initial cost for masks, but in high volume the ongoing cost is reduced by 30–40% vs. 200-mm wafer. The actual numbers are influenced by such commercial issues as volume pricing—I don’t pay $1000/wafer if I buy several hundred wafers—but it should be apparent that at 1 square millimeter, the chip cost is a substantial fraction of the $0.05 tag cost goal promulgated by such organizations as EPCglobal. It is imperative to keep the chip as small as possible to minimize IC cost.

Traditionally, the size of digital ICs has been strongly influenced by scaling: the reduction in the size of transistors due to improvements in lithography and processing, which results in a reduction in the size of the chip for the same number of transistors. Technologies are usually named for the smallest feature size used in the process: for example, a typical high-speed fabrication process might make use of an 0.13-μm line to form the transistor gate, and would generally be referred to as an 0.13-μm process. For many years, scaling the size of the transistor down also resulted in reduced power consumption per transistor. However, there are some obstacles to achieving the benefits of scaling in RFID chips over the next several years. First of all, the most advanced process technology is always expensive. It is much cheaper to purchase masks and wafers for 0.18-μm processing than for 0.13-μm processing. Secondly, the benefits of scaling are decreasing as fundamental limits in process technology are reached. For example, silicon dioxide films, critical for forming MOS transistors, have reached thicknesses equivalent to only about 3 molecular layers and can’t be reduced much more. Efforts to replace silicon dioxide in this role have so far been unfruitful. Because of leakage through these thin oxide films, power consumption in very small devices is also not as small as one might have expected from extrapolation from older technologies.

A substantial fraction of an RFID IC consists of analog functional blocks: RF rectifiers for power supplies, capacitors for energy storage, and circuitry for decoding and modulation. The size of analog blocks doesn’t necessarily change just because the minimum feature size is reduced. For example, the area required for a storage capacitor is set by the total power consumption of all the chip features, so if power consumption doesn’t go down, the capacitor must remain the same size. A diode’s size is set by the parasitic resistance and capacitance associated with it, which determine the frequency it can operate at and the impact it has on the antenna match. A modulation capacitor’s size is set by the characteristics of the antenna and the modulation efficiency we seek to achieve. Protection circuitry requirements are determined by the largest voltage the tag expects to see, not by the smallest voltage its transistors could operate at. While in general, the size of the analog blocks can shrink if the power consumption of the logic they support is reduced, analog functions usually don’t scale down in size nearly as readily as the corresponding digital circuitry.

So, we can’t expect scaling alone to magically reduce IC costs. It is also important to exploit every possible measure to reduce size and power consumption of the logic blocks. Automatic routing of wires between transistors is fast and convenient, but clever human designers can squeeze space out of the design by (laborious) manual optimization. Power consumption in the logic circuitry can be reduced by operating the devices near the threshold voltage (the minimum voltage to turn the transistors on), but threshold voltage differs from one chip to another due to variations in manufacturing and due to temperature variations in operation. It is possible to use onboard nonvolatile storage to adapt the operation of each chip to its conditions. Such threshold adjustment techniques may also allow the use of MOSFETs instead of junction diodes or expensive Schottky diodes for rectification.

Finally, a tag IC has a number of logic blocks, all running from a very high-impedance antenna (that is, an antenna that has a hard time supplying much current). Each time a logic gate switches its state, a transient current flows from the local power supply connection. If the local supply voltage fluctuates as a consequence—that is, if decoupling is insufficient—the change could be interpreted by a nearby gate as a logical input, leading to errors in operation of the circuit. The challenge of properly isolating the individual gates and the segments of the circuit, is much larger than in conventional circuit design, where power at a reasonably fixed voltage is available from a battery or power supply.

Packaging: No Small Matter

So far we’ve focused on the electrical guts of a passive tag, but the physical construction is also of great importance. The IC must be connected either to an intermediate strap or the substrate itself, the latter formed of plastic or paper, at the same time making electricalcontact to a separately created antenna structure. At this stage, the tag is often called an inlay. The inlay can be used on its own, either as is or coated with adhesive to be attached to an object. Alternatively, the inlay can be laminated between sheets of paper or plastic to form a smart label or a smart card. These alternative fates are depicted in Figure 5.24.

As a consequence, the overall manufacturing process for a typical smart label containing a passive tag looks something like that depicted in Figure 5.25. In the remainder of this section, we will briefly examine each of these steps.

More has been written about silicon CMOS fabrication than is prudent to contemplate, and we shall not attempt to recapitulate such an extensive field in this brief aside. We shall content ourselves with reemphasizing the role of IC size in determining IC cost: the total cost of a completed wafer is roughly independent of what is on it, so the smaller an IC chip is, the more you get per wafer as long as most of them work. High yield of good devices is also very helpful in minimizing test costs. If a large percentage of chips fails, it is necessary to test carefully at the beginning of the process to minimize the labor and materials wasted on bad devices, whereas if only an occasional failure is encountered, testing can be postponed to the end, reducing total cost. Yield is influenced by a plethora of factors, including process design and equipment maintenance in the wafer fabrication facility, and thoughtful design practices.

Historically, a completed IC connects to the outside world by providing square pads 100 microns or so on a side at the edges of the chip. The chip is placed in a plastic or ceramic package, and electrical connections are made by wire bonding: one end of a gold or aluminum wire around 25 microns (0.001") is bonded to the IC pad using ultrasonic excitation to scrub away surface layers and the other end to a similar contact pad on the package. Wire bonding is highly automated, fast, and reliable. However, it is intrinsically a serial process, with each bond made in sequence, and thus, relatively expensive when the target is a $0.01 chip.

Fortunately, an alternative means of connecting ICs to the outside world is available. This approach, variously known as flip-chip or chip-scale packaging, involves the formation of thick metal bumps on top of the contact pads on the IC. The chip is inverted, and the bumps are placed onto corresponding conducting regions in a package, strap, or tag antenna.

Much early work in this area was performed by IBM and made use of evaporated lead and tin to create conventional solder bumps. (Solder, a tin-lead alloy, melts at around 220◦C, and has historically been widely used for wiring and interconnections, although concerns about the environmental impact of lead have resulted in increasing use of lead-free alloys.) Solder can also be electroplated. The solder-bumped chip is placed over an array of plated or freshly cleaned copper pads and heated to melt the solder, which then forms a ball (Figure 5.26). The molten solder balls wet the exposed plating or copper surface, and surface tension draws the chip into the proper alignment with the pads. Many alternative metal systems can also be used for forming bumps, including both fusible bumps—bumps that melt at low temperature, like solder—and nonfusible bumps. Non fusible bumps can be formed, for example, using electroless nickel plating followed by electroless gold plating. (Electroless plating solutions exploit local chemical reactions to cause metal to deposit onto an exposed conducting surface from the solution and can be used to selectively deposit metals onto conductive regions while leaving insulating regions untouched. A completed IC chip can be passivated with an insulator, leaving only the bond pads exposed, and then immersed in plating solution; bumps will form only where the bond pads are, avoiding the need for a separate masking step like that used in evaporative solder definition.)

Melting bumps requires high temperatures, which may exceed the tolerance of the inexpensive plastics used for passive tag assembly. A popular alternative is to use non fusible Figure 5.26: Cross-sectional View of Solder Bump After Reflow; Ball Diameter Typically 100–200 microns. bumps and conductive pastes, typically fabricated by mixing fine metal particles, often of highly conductive silver, with a polymer binder, typically an epoxy resin. It is possible to replace the metal bumps with conductive paste, applied by screen printing, or to use conductive pastes to make contact between bumps and the antenna or strap pads. A perhaps more useful approach is to use metal bumps in conjunction with anisotropic conductive adhesives (ACAs) (Figure 5.27). An ACA is a conductive polymer with carefully adjusted proportions of metal and binder so that the material is conductive when compressed but not in its default state. If a layer of ACA is placed between a bumped chip and contact pads and the chip pressed against the adhesive during cure, the compressed regions under the bumps will become conductive and the remainder of the adhesive will be insulating, forming a self aligned conductive contact to the underlying pads. Such a scheme avoids the need to accurately align the bumps, conductive paste, and pads. ACAs are used in flat-panel display assembly for the same reason. Isotropic conductive adhesives are less expensive and may use lower cure temperatures, but require more accurate assembly, and are more likely to be used in attaching the strap to the inlay, where alignment tolerances are less crucial.

Because tag ICs must be physically small, separating them becomes an important issue. Large ICs, such as microprocessors or memory chips, are separated from their parent wafer using a saw with a narrow blade to slice the wafer up into rectangular blocks, each containing a chip. Kerf loss, the amount of silicon removed by a conventional wafer saw, is around 100 microns. This is equivalent to expanding the chip on all sides by half of the saw kerf: a 1×1 mm chip becomes a 1.1×1.1 mm chip, with an area of 1.2 mm2: a 20% increase in the cost of the chip. Kerf loss can be reduced if the wafer is reduced in thickness, typically by grinding the back side, before the individual dice are separated.

Alternative processes for die separation can also be considered. Chips made of gallium arsenide and other compound semiconductors are often separated by scribing: a diamond-tipped stylus cuts a linear notch between each row or column of chips, and then the wafer is bent or stretched slightly to cause it to break along the scribed lines. This process works extremely well for small ICs on these materials, because they are more delicate than silicon, and also break readily in certain directions (known as cleavage planes). Scribe and break can also be used for silicon devices, but silicon is much stronger than gallium arsenide or indium phosphide, and thinning the wafers is indispensable to achieve good separation. Scribing also tends to cause mechanical damage and particle problems.

Another alternative is to use a corrosive liquid to etch the material between the ICs away. Etching produces smooth surfaces and no mechanical damage but requires some sort of mask to protect the ICs themselves from the etchant: an additional step with additional labor and materials costs. Etching solutions can be either isotropic (etching at an equal rate in all directions) or anisotropic (etching most rapidly in certain directions with respect to the underlying silicon crystal lattice). The kerf loss due to an isotropic etch used for die separation is about twice the thickness of the material being etched since the etchant proceeds sideways at the same rate it proceeds downwards, so again it is useful to thin the wafers before attempting to separate the dice. Anisotropic etchants reveal specific crystal planes and may allow a more efficient use of the wafer area, but are usually slower than isotropic etches.

Once the individual ICs are separated, they may be assembled onto an intermediate strap prior to attachment to the inlay. In this fashion, the relatively high-precision strap attach can be done in a specialized facility, and the lower-precision strap-to-tag attach, which is unique to each tag design, can be performed separately, using isotropic conductive adhesives and standard assembly techniques.

Alien Technology has pioneered the use of fluidic self assembly to place large numbers of chips precisely onto their straps. Because the chips are not handled mechanically, the kerf between chips is limited by the separation process only and can be as small as 20 microns using anisotropic etching of a thinned wafer. The separated chips are released into a fluid carrier from which they self locate onto precision-etched openings in an intermediate support structure, a strap web. The configuration of the chips and openings ensures that the chips lie right-side-up. The chip-support structure is then laminated, and openings are cut in the Figure 5.28: IC Attached to Strap in Preparation for Mounting on Antenna. laminate to permit contact using a printed conductive material. The resulting conductive straps can couple to a nearby antenna to permit non contact preliminary testing of the parts before assembly. Other vendors use more conventional assembly techniques using automated pick-and-place equipment.

Once the chip is placed on a strap, it must be assembled to make an inlay. The inlay is usually constructed from plastic; a common material polyethylene terepthalate (PET). PET is an inexpensive, mechanically robust plastic with good resistance to most common chemicals and low dielectric constant (which helps in antenna design). It is widely used in textiles, capacitors, recording tapes, and other applications. Polyimides are also used.

An antenna must be constructed on the inlay. The standard means for producing patterned conductive materials on plastics, taken from the printed circuit technology in wide use in nearly all electronic products, involves electroplating a thin copper layer onto the plastic, and then applying a mask to protect the regions where the metal is to remain and removing the undesired copper with a liquid etchant. This type of subtractive-etching process is mature and robust and produces films with excellent conductivity. Copper thicknesses of 10–40 microns are readily achieved, corresponding to sheet resistances of less than 1 mΩ/square. (Sheet resistance is the resistance of a square piece of a thin material with contacts made to two opposite sides of the square. It is independent of the size and depends only on the material and thickness, and is numerically equal to the resistivity of the film divided by its thickness. The resistance of a line may be estimated by multiplying the sheet resistance by the aspect ratio of the line; for example, a line 5 cm long and 1 mm wide has an aspect ratio of 50, and using material with a sheet resistance of 1 mΩ/square would have a DC resistance of 50 mΩ.) Metal may also be patterned by stamping—that is, cutting the requisite pattern out of a foil with a sharp-edged tool—and adhering to the plastic.

A significantly simpler and less expensive approach is to use a conductive paste to form the antenna. In order to get good performance, high conductivity materials must be used. Modern conductive inks, made using silver particles embedded in a specialized polymer matrix, achieve bulk resistivity of 30–60 μΩ-cm, about 10 times higher than solid silver or copper but acceptable for tag applications. Corresponding sheet resistances are around 12–20 mΩ/square. A typical tag antenna segment with an aspect ratio of 20 will thus add a DC resistance of around 0.4 Ω, negligible for most antenna designs. Surface roughness is also important since at UHF frequencies, most of the electrical current flows in a layer a few microns thick near the surface of the film. Recent films have shown improved surface roughness and better RF performance. Challenges for conductive ink assembly include susceptibility to corrosion and oxidation and problems achieving reliable attachment of the IC.

Whichever approach is used, it is necessary to use high-speed volume manufacturing techniques to minimize cost. The inlays are generally fabricated on long continuous rolls of plastic, using specialized high-speed patterning and assembly equipment.

Once the IC or strap is assembled onto the inlay/antenna structure, polymer coatings may be applied to protect the IC and antenna. If the inlay is to be used on its own, it may receive an adhesive coating on the backside and be laminated onto a paper backing. Inlays are also often laminated into a conventional paper or plastic adhesive-backed label; this process is often known as label conversion, with a smart label being the result. Such labels are usable in specialized printers that both print the human-readable printed labeling and write and verify the ID of the encapsulated tag. The resulting labels may be automatically applied using a label applicator, or applied by hand.

Inlays incorporated into labels or rolls must be able to tolerate bending, rolling, and compression during the printing and application processes, as well as electrostatic discharge resulting removal of protective layers for adhesive application, and from general handling.

OtherWays

The current author has never tried skinning a cat and has no idea if a preferred method exists or the advantages accruing to such relative to alternative approaches, or whether the latter would be more common in other universes with slightly different physical laws. However, there are unquestionably alternatives to fabricating a UHF RFID tag using a silicon IC at its heart.

The most extensively explored of these approaches is the surface acoustic wave (SAW) tag. You may recall that we have already briefly introduced SAW devices in connection with filtering RF signals (see Chapter 4, Section 4.3.4). In such a device, an electrical signal (from the antenna) is converted into a sound wave, using a set of periodic metal electrodes known collectively as an interdigitated transducer (IDT), constructed on a thin slice of a piezoelectric material such as quartz or lithium niobate. The sound wave propagates much more slowly than the speed of light, so at UHF frequencies wavelengths are a few tens of microns, making it straightforward to construct arrays of electrodes spaced at integer half-wavelengths. Once the wave is launched away from the transducer, it travels away to the far end of the slice, not terribly interesting by itself. However, if we place an additional electrode along the propagation path, the acoustic properties of the near-surface region are slightly modified, and a portion of the wave will be reflected, just as a water wave can be partially reflected by an object floating on the surface of the water (Figure 5.30). When the reflected wave reaches the IDT, it creates a small voltage in the antenna, and thus, launches a tiny delayed scattered pulse. By adjusting the pattern of these electrodes, a coded message can be sent, containing (for example) the unique ID of the SAW tag.

In order to detect the delay in the pulse, the reader signal must typically be time dependent. The reader may transmit a pulse, or a signal whose frequency increases or decreases with time (a chirped signal) may be used. Let’s examine the case where a pulse is used. The length of the SAW chip (which, just like a silicon IC, has an important influence on its cost of manufacture) is determined by the time delay it must support: the longer the chip, the more time it takes for the sound wave to get to the end and the more room there is for adding reflectors. The number of reflectors is determined by the requirement that they be separated in time by something comparable to a pulse width: if a pulse is (say) 100 nanoseconds long, successive reflectors ought to be separated by a distance that takes around 100 nanoseconds for the sound wave to cross. The more reflectors we have, the more data we can store on the chip. So short pulses are best.

If we build a chip with a round-trip delay of 1 microsecond, and use 100 nanoseconds pulses, there is room for roughly 10 reflector electrodes (perhaps, fewer since we may need to use one to mark the beginning of the pulse train); if each electrode position encodes 1 bit through an electrode being present or absent there, we have a 10-bit ID, hardly adequate for most applications. To get to a full 96-bit ID with 16-bit error check, we need a delay of 11 microseconds. For a typical sound velocity of around 4000 meters per second, the round-trip delay of 11 microseconds corresponds to a chip length of 2.2 cm—substantially larger than the Si IC sizes discussed in the previous Section. In SAW tags, the size of the ID space is directly traded against the size (and thus cost) of the chip.

To mitigate the situation, we can use shorter pulses or encode more bits in each pulse. The problem with shorter pulses is that short pulses use bandwidth. Recall that in Chapter 3, Section 3.3, we noted that the faster the modulation, the more bandwidth is used. To produce a pulse that lasts 100 nanosecond, we need around 10 MHz of bandwidth. But the amount of bandwidth is limited by regulation: in the United States, only 28 MHz is available in the 902–928 MHz ISM band, and much less is available in other jurisdictions. To get better performance, it makes more sense to operate at 2.4 GHz, where about 80 MHz is available for unlicensed use in the United States and tens of MHz in most other areas of the world. To encode more bits per reflector, we can use pulse-position modulation, in which we try to resolve small displacements in time of the successive reflections. A more powerful but more complex approach is to detect not only the amplitude and timing of a reflected pulse but also the relative phase of the RF signal. Phase detection is equivalent to detecting the location of the reflector to within a fraction of an RF cycle. At 4000 m/s, one 2.4-GHz RF cycle is equivalent to 1.7 microns, so by using phase detection, we acquire a very high-resolution view of the electrode position, at the cost of a very stringent requirement on the position of each electrode on the chip.

The great advantage of a SAW tag is that there is no logic to power on the tag chip, so the read range is limited by the reverse link budget only. The mature techniques of pulsed radar design can be applied to the reader, providing good sensitivity in the presence of high-amplitude pulses. Long reverse-link-limited read ranges can be obtained. SAW tags can be placed close to metal objects or aqueous fluids (conditions where the available electric field from the reader is reduced) and still be read because there is no requirement for a minimum power at the tag.

On the other hand, SAW tags have no logical capabilities and can only reply with a stereotyped pulse string. All intelligence must be incorporated into the reader. The lack of responsiveness becomes a challenge when multiple tags are present in the region being examined by the reader. Since the tags can’t receive and interpret instructions, all will respond, generally leading to an incomprehensible collision between the tag responses. Various approaches to solving the collision problem are available: the reader can take the strongest tag first, decipher the signal (if there aren’t too many others), and then subtract that signal from the whole and go after the next strongest. Directional antennas can be used to limit the physical region being interrogated; this approach requires use of 2.4 GHz or higher frequencies, as highly directional antennas at 900 MHz are quite large and unlikely to be practical for indoor use. Tags can be designed with built-in fixed delays, so that they respond at different times and don’t overlap, but this approach sacrifices code space and thus, raises tag cost for the same number of bits of information. Combinations of all these approaches are also possible. It is apparent that when only a few tags are present, collisions will be readily dealt with by a combination of the techniques above with appropriate procedures, but that if tens or hundreds of tags are to be read, an IC-based approach is likely to be superior.

A second alternative to which we shall devote some brief consideration is the use of organic materials to construct an electronic circuit. Semiconductor devices, upon which all silicon ICs are based, exploit the fact that silicon (and certain other materials) can exhibit substantial electrical conductivity when a pure sample is doped with an appropriate alloying element. These dopants either contribute an electron to the crystal lattice or extract an electron from it (leaving behind a positively charged hole); the two kinds of dopants are known as n-type and p-type, respectively. The free electrons and holes that are created by the dopants can move through the silicon, allowing electric currents to flow, and can be reversibly driven away from some regions of the material through the use of electric fields, allowing a voltage to control a current flow, and thus, enabling the operation of transistors. To make an IC rather than just a transistor requires the additional capability to fabricate basic electrical components: wires, resistors, capacitors, and (less often) inductors. Since the invention of the transistor in 1947, and more significantly of the planar IC in the early 1960s, hundreds of billions of dollars have been invested in the technology to design, fabricate, test, and use silicon IC. Any alternative technology must surmount the very substantial competitive obstacles presented by the need to functionally replicate this vast infrastructure.

The idea of replacing the silicon IC (and possibly the antenna as well) in an RFID tag by conductive organic materials is of interest because of the belief that such an approach will eventually enable the use of very high volume, very low cost processes such as printing and lamination to create RFID tags. Most plastics are insulators, being made of exclusively covalent bonds; but it has long been known that organic materials can provide substantial electrical conductivity when structures encouraging the formation of delocalized electron states are used; graphite (pure carbon organized in a planar structure) is the archetypal example. Graphite is, however, mechanically awkward, and a poor choice for wiring or circuitry. Polymeric materials with unsaturated or delocalized bonding are more plausible candidates for materials with substantial electrical conductivity and the desirable properties of plastics. Organic conductors have been under active development since the 1960s.

Certainly a great deal of progress has been made in organic conductors since the current author laboriously grew miniscule crystals of TTF-TCNQ (the stylish candidate of that ancient day) for his undergraduate thesis. Modern materials, such as vacuum-evaporated pentacene (a block of five hexagonal benzene rings sewn together at the edge, for those who care) display electron mobility—the response of an electron to an imposed electric field—of 1 to 10 cm2/V second, much less than achieved in bulk silicon (where mobilities in the hundreds are the norm) but quite comparable to the performance of amorphous silicon materials that have seen wide commercial use in active-matrix flat panel displays. Doping is difficult but possible. Transistors can be fabricated using inkjet printing or spin casting techniques, though vacuum sublimation produces better material properties. Working tags at LF (125 kHz) have been demonstrated, though at the time of this writing it appears that only certain components of a 13.56 MHz tag have been constructed. Rectification (needed to generate power for the IC–see Section 5.2 of this chapter) has been demonstrated at up to a few 10s of MHz but not at UHF frequencies.

There are very substantial obstacles to commercial deployment of these techniques. Operating voltages are typically 10–20 V, much higher than the 1 to 3 V used in silicon ICs. To achieve even such voltages requires that feature sizes around 3 microns be resolved in the structure. Such resolution, roughly equivalent to 8500 dots per inch, is much finer than that normally achieved in low-cost printing processes. The electrical properties of the polymers used today are often unstable in use and on extended exposure to air. The best semiconductor layers are formed by vacuum techniques at a rate of around 0.1 molecular layer per second, not conducive to high throughput or low cost.

Reliable production equipment and processes must be developed for high volume fabrication, a very considerable investment if quantities of hundreds of millions to billions of tags are envisioned.

Even if all these technical hurdles are overcome, challenging economic hurdles remain. At the time of this writing, a 512 MB DRAM chip costs around $6, which is equivalent to around 11 nanodollars (!) per bit or very roughly 0.25 nanodollar per printed ‘dot’, the actual value varying somewhat depending on the memory structure used. A tabloid printed in moderate volume on 18��×12�� (47 × 31 cm) paper at 200 dpi (8 dots/mm) costs around $0.20/copy, resulting in a cost of 3 nanodollars/dot. Larger-volume printing costs are about 10 times lower, or 0.3 nanodollars/dot. That is, the cost of conventional printing with inks whose basic formulation is centuries old is if anything more expensive per feature than the cost of modern silicon IC fabrication. It is very unlikely that the exotic materials using in making a low-voltage printed organic IC would achieve these cost levels in the near term. Printing an IC only seems cheap if we assume that the IC complexity is comparable to the complexity of printing a bar code. When we include the magnitude of the actual task to be undertaken if organic circuitry is to provide functionality comparable to its silicon counterpart, it is no longer very clear that printing offers a substantial cost advantage.

Some work has also been done in identifying objects using conductive materials or fibers with no circuitry whatsoever, relying on the frequency-dependent behavior of radio reflection from these antenna-like strands to distinguish one object from another. Such an approach promises a very low cost for the ‘tag’ structures, since they contain no circuitry of any kind. However, a sophisticated reading device using millimeter-wave frequencies (>10 GHz) is needed, and since the ‘tags’ have no logic capabilities, usage models are constrained. At these high frequencies, diffraction is much reduced compared to the 900 MHz band, and the advantages of non line-of-sight operation are lessened. Such circuit-less tag technologies may find special niches where their very low ongoing cost makes up for complexity in implementation. Non RF-based techniques for authentication, using chemical compounds with unique optical or other analytical signatures, are also used and may have advantages over RFID in this type of application, though such approaches hardly seem adaptable to unique item serialization.

Capsule Summary

Passive tags harvest power from an incident RF signal using diodes arranged to form a charge pump. Multiple stages help boost the output voltage to the level needed to power an IC, but a practical limit exists to the extent to which circuitry can be used to compensate for low peak voltages received from the antenna. Multiple stage charge pumps are rather inefficient, converting less than half of the received RF power to useful DC power for the remainder of the tag circuitry. A similar rectifier or charge-pump configuration with a faster response is used to extract the amplitude envelope of the reader signal, wherein can be found the commands and data from the reader.

Tags talk back using backscatter modulation. There is an inevitable tradeoff between the extent to which the scattered power is modulated and the amount of power retained to run the tag. The best balance between these competing alternatives is obtained by changing not the resistance attached to the tag antenna but the capacitance. Backscatter efficiency of –3 dB can in principle be obtained with modest effects on the tag power supply (but actual results depend on the provisions for matching tag antenna to IC load).

While the logical processing required by a typical protocol is modest compared to modern processor capabilities, design of tag ICs is unusually challenging due to the intersection of two stringent constraints: very low cost and marginal power. Careful attention to individual aspects of the design, including hand routing and analog simulation, is required.

A tag is more than just the IC. Assembly of the tag combines an IC, strap if used, antenna, substrate, and optionally label. Assembly is usually based on forming contact structures (bumps) on the IC to mate to contacts on the strap or antenna. Printed or etched metal antennas have historically dominated, but antenna fabrication via printed conductive inks shows promise for UHF applications. The IC, strap, antenna, and substrate form an inlay, which may be laminated into a printable and thus human-readable label to be used.

Exercises

Rectifiers:

1. We treated a diode as a very simple object that has no current flow until the voltage exceeds +VON and unlimited current flow with no additional voltage thereafter. Real diodes are somewhat more accurately represented by equation (5.1), repeated here for convenience:

where the product q/kT is about 38.5 at room temperature. Let I0 = 10−15 A. What voltage across the diode will produce a diode current I = 1 microamp? What voltage is needed to achieve a diode current b>I = 10 mA? What error in voltage have we made by using an on-voltage of 0.5 V?

V(1 μA): ___________ Error vs. VON: _____________

V(10 mA): ____________Error vs. VON: _____________

2. We examined the use of voltage doublers to increase the output voltage of the rectifier stages. An alternative approach is to use a full-wave rectifier circuit. A possible equivalent circuit for a full-wave rectifier attached to an antenna and load is shown below. Using the idealized diode model of Figure 5.3, find the output voltage for a given input voltage. Compare it to the output voltage of a doubler (equation (5.6)).

Backscatter modulation:

3. An alternative way of imposing an modulation on a tag antenna is shown below. Assume that the radiation resistance and load resistance are both 100 Ω, and that the circuit is operated at 915 MHz. Let the modulation capacitor value be 1 pF. Find the complex impedance of the circuit in the modulated state (when the capacitor is not shorted out). Appendix 3 may be helpful. What is the magnitude of the current that flows through the circuit when the capacitor is present compared to that when the capacitor is shorted? What is the relative phase?

magnitude __________________ phase __________________

Find the power absorbed in the load in the modulated state as a fraction of Pav.

____________________________ normalized power, modulated state

Find the average normalized load power, assuming the modulation occupies the two possible states with equal probability.

____________________________ normalized power, average

Subtract the complex value of the current through the radiation resistance when the capacitor is present from the current amplitude when the capacitor is shorted to find the change in current due to modulation. Find the absolute magnitude of this current, and square it and multiply by Rrad/2 to find the radiated power.